资源列表
lcd_verilog
- LCD显示模块的编码，可以FPGA的LCD显示屏上显示文字-LCD display module coding FPGA LCD screen to display text
fre_count
- fpga频率计altera DE2开发板调试通过-fpga altera DE2 frequency count
Verilog-trafficLights
- 使用格雷码和one-hot码设计的交通灯程序-Gray code using traffic lights and one-hot code design
clock
- 数字时钟的实现，数码管显示，实现时分秒的显示(The realization of the digital clock)
1
- VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，序列检测器的设计，一般状态机等等。(VHDL code, some textbooks for small programs. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3 prio
8_LigWater
- FPGA，VHDL语言 ：分频1S 8位流水灯，适用于所有FPGA芯片，VHDL源程序-FPGA, VHDL language: divide-1S 8 light water, and apply to all FPGA chip, VHDL source code! !
CDMA_MULT3_ise9migration
- CDMA Source code and documentation
simpleCPUdesign
- 本文档介绍了一个简单的单周期CPU，和流水线CPU的实现过程。 这是我们完成伯克利大学EECS系计算机系统结构课程的实验文档，实验信息见http://www-inst.eecs.berkeley.edu/~cs152/fa05/-This document describes a simple single-cycle CPU, and CPU pipeline implementation process. This is the complete Berkeley EECS Departme
verilogiic1121
- 本程序是基于verilog HDL的iic程序，需要的下载-This procedure is based on the Verilog HDL IIC procedures, the need to download
QuartusII_Usage
- 这是一个关于VHDL开发环境QUARTUS的电子书，里面详细的介绍了QUARTUS的使用。-This is a development environment, Quartus VHDL about the e-book, which describes in detail the use of Quartus.
Encoder
- VHDL Beispiel für Encoder
QuartusII
- QuartusII基本使用方法，简明扼要，很适合初学者学习使用-QuartusII basic use, concise, very suitable for beginners to learn to use