资源列表
Test
- verilog shift register code
CRC-generator
- 提出了一种32位并行和高度流水线的循环冗余码（CRC）发生器。 该设计可以处理5个不同的通道，每个输入速率为2Gbps（总输出吞吐量为5x4Gbps）。 生成的CRC与32位以太网标准兼容。 该电路已经在0.35Micron标准CMOS工艺中使用标准单元实现，其使用Galois Fields的特性，并且被认为是“自由的”IP。-A 32-bit parallel and highly pipelined Cyclic Redundancy Code (CRC) generator is
PWMkongzhiLEDxianshi
- 实现PWM 输出控制LED 显示。通过这个实验，掌握采用Verilog HDL 语言 编程实现PWM 输出控制LED 的显示方法以及PWM 控制的工作原理。-PWM output to control LED display. Through this experiment, master PWM output to control LED display as well as the works of the PWM control using Verilog HDL language p
shu_ma_guan_xian_shi
- 基于FPGA的开发小实验，主要是数码管的静态显示相关资料和源代码，具有一定的参考价值。-FPGA-based development of small experiments, static digital tube display relevant information and source code, has a certain reference value.
DSB_test_cordic
- 針對通訊中的dsb系統做硬體模擬的實現與驗證希忘的大家有一定的幫助謝謝 -For communications in the dsb system so the realization of the hardware simulation and verification of the Greek forget we have some help Thank you
FIFO
- 流水车间2机FIFO实现，WIP的显示，及加工时间的显示-Use this program to show the number of WIP and the process time in flow shop which use the fifo rule to work.
NET2
- FPGA中DM900A以太网控制器驱动程序开发-FPGA, DM900A Ethernet Controller Driver Development
wodeshji
- 在FPGA上，实现了一个多功能数字抢答器，设置四个抢答按钮，及若干控制台按钮，有计分，抢答，重置，及时等功能-In the FPGA, the realization of a multi-functional digital Answer, and set up four Answer button, and a number of console button, there are points, Answer, replacement, and other functions in tim
counter_0-to-9999
- 数码管计数，在数码管上计数，从0计到-Digital counting experiment, the digital count on, count from 0 to 9999
74HC151
- IC VHDL 集成设计 IC VHDL 集成设计-IC VHDL design
led_sport
- vhdl流水灯程序，spartan-3e 简单应用-vhdl light water program, spartan-3e simple application
lcd2
- 又一个用vhdl编写的lcd驱动程序，完美运行，直接下载。-lcd