资源列表
poc04008307
- 设计一个并行输出控制器，可以连接系统总线和打印机- The purpose of this project is to design and simulate a parallel output controller (POC) which acts an interface between system bus and the printer.
7_ren_biao_jue_qi
- 用vhdl,设计的一个七人表决器，当赞成人数大于等于四时显示表决通过，同时分别将投票中赞成的人数和反对的人数在数码管上显示出来-VHDL design of a seven-vote in favor of the number of greater than or equal to four o' clock, the vote at the same time, respectively, displayed the number of people vote in favor of
VHDLPWM
- fpga输出pwm的vhdl程序，已经过开发板试验，绝对可用,包括所有文件。-fpga vhdl output pwm' s program has been developed plate test, absolutely free.
ddr3_top
- xilinx DDR verilog 控制器-DDR verilog controller FOR XILINX
Modelsim
- modelsim 的使用说明，新手上手最佳手册-modelsim' s instructions, the best manual for novices to get started
taxi
- verilog实现出租车计费功能，起步价、里程数、等待时间计算-Verilog taxi meter function, starting price, mileage, waiting time
shuzizhong
- 这时用VHDL语言编写的多功能数字钟，具有正常的计时功能，还能进行校时、校分，并且具有整点报时功能-Then with the VHDL language multi-functional digital clock, with the normal timing functions, but also to the school, the school hours, and have the whole point timekeeping function of
test_uart
- 原创的altera de2-70 FPGA板功能测试实验，用于UART的读写。包含完整源代码，仿真文件，可直接下载到板子上的SOF文件，适合初学者研习。-Original altera de2-70 FPGA board function test, used for UART read and write. Contains the complete source code, the simulation files, can be directly downloaded to the boa
frequency
- 等精度频率计（FPGA部分），通过单片机发送频率控制字给FPGA，FPGA实现计数，再将计数结果发送给单片机后进行数据处理最后发送到数码管或液晶屏显示待测频率-Precision frequency meter (FPGA part) by the single-chip transmit frequency control word to the FPGA, FPGA, to achieve the count, and then finally sent to the digital dat
vga256
- vga显示256色彩，verilog hdl编写-256color display by vga,write in verilog
qsys_design
- altera Qsys使用说明，陪了一个简单的例子，供参考-the altera Qsys Instructions accompany a simple example, for reference
LED_shanshuo
- 基于FPGA的小实验，是一个LED的闪烁，文件中有学习的资料和相关源代码，具有一定的参考价值。-FPGA-based experiments, an LED flash, learning information and source code files, has a certain reference value.