资源列表
ArhivaAdrian
- Anticipated Adder for Xilinx
fsq
- 利用VHDL语言实现信号发生器。 -VHDL SIGNAL GENERATE
LCD12864_TEST
- VHDL语言，１２８６４显示屏的驱动程序，本人已在自己开发板上测试成功，需要的朋友下载后根据自己的开发板稍加修改即可-VHDL, 12864 display driver, I have tested successfully in my own test board, you need slightly modified according to your own test board
coa
- 在Modelsim中实现类MIPS多周期流水化处理器-In Modelsim achieve class multi-cycle pipelined processor MIPS
FIFO
- 一个先入先出FIFO的VHDL实现，程序经过了编译验证。-A FIFO FIFO to achieve the VHDL, verification procedures have been compiled.
Lab6(result)
- VHDL的小程序，可实现4bits输入的循环-VHDL small procedures, can enter the cycle 4bits
fpga
- 电子密码锁的相关程序，很好很耐用！但水平有限啊-Electronic combination lock procedures，
VHDLdesignexamples
- 半整数分频器、音乐发生器、信号产生器、多功能电子表、交通控制灯、数字频率计的设计实例及习题-Half-integer divider, music generator, signal generator, multi-function digital watch, traffic control lights, digital frequency meter design examples and exercises
music
- 蜂鸣器实现播放音乐，两个按键可选择播放，共三首音乐可选。Xilinx ISE 9.1环境下工程。-Buzzer for playing music, playing the two keys to select a total of three songs optional. Xilinx ISE 9.1 environment projects.
02.PmodDA2
- DAC转换器状态机 基于xilinx FPGA-The DAC converter state machine is based on the xilinx FPGA
combinationalcircuits
- vhdl编程国外教程，英文版，组合逻辑集成电路编写-vhdl programming tutorial abroad, in English, prepared by combinational logic IC
QAM16MapandDemapping
- 包含QAM16的调制与解调的整个工程，并且还有Testbench-Contains QAM16 of modulation and demodulation of the entire project