资源列表
shejibaogao
- 描述的是一个时钟在vhdl上实现的全过程，且含实验报告-Describes a clock in the whole process of the VHDL realization, and contain the experiment report
COUNTER.ZIP
- 4 bit counter example for CHDL beginners
Waveform-generator(DAC902)
- 信号发生器可1Hz - 10MHz 可调频调幅产生ASKPSK-Waveform generator(DAC902)
FIR_lowpass_part
- 实现FIR滤波器的并行算法，这里是一个64阶的低通滤波器-FIR filter of parallel algorithm
kp_verilog
- veriog 实现求逆模块 加仿真结果 shi henyong-verilog is useful in finite field
5.1-1602
- 1602字符液晶显示程序，用来完成液晶的显示，基础的那种-1602 character LCD program, to complete the liquid crystal display based on the kind of
SDRAMDriver
- sdram接口驱动，按照datasheet基本指令顺序开发，极易理解，但功能上存在一定局限性-sdram interface driver, in accordance with the development of the datasheet basic instruction sequence, easily understood, but there are certain limitations on the functions
usb_Phy
- usb1.1 VHDL源码，主要描述收发数据过程-usb1.1 the VHDL source code, descr iption of the send and receive data process
counter
- 用4个T触发器组成16位的计数器，FPGA实验ALTER DE2开发板自带光盘的案例程序解析-Four T flip-flop 16 of the counter, the case of FPGA experiment ALTER DE2 development board comes with CD-ROM program parse
clocker-and-timer
- 时钟与计时器，FPGA实验alter DE2开发板自带光盘的案例教程编程解析-Clock and timer, FPGA experimental alter the DE2 development board comes with the CD case tutorial programming resolution
latches-
- 锁存器，FPGA实验alter DE2开发板自带光盘的案例教程编程解析-Latch, FPGA experimental alter the DE2 development board comes with the CD case tutorial programming resolution
Finite-State-Machines
- 状态机，FPGA实验alter DE2开发板自带光盘的案例教程编程解析-State machine FPGA experiments alter the DE2 development board comes with a CD case tutorial programming resolution