资源列表
LabALU
- vhdl编写的8-bits ALU,包括加减法与或非6种工作模式-vhdl write 8-bits ALU, including the addition and subtraction and non-operating mode 6
Jewish
- 乍一看书名，许多读者可能会感到奇怪：为什么说左手犹太人右手温州人呢？为什么不是其他人？近二千年来，即使有颠沛流离，即使被驱赶打压，犹太商人还是整个商业世界的龙头老大，漫长的历史长河中，印度商人、中国商人、*商人都曾风云一时，但他们都只能屈居于犹太商人的阴影下。-At first glance the title, many readers might wonder: Why is the Jews left hand Wenzhou it? Why not others? Nearly two
fft
- Quartusii的FFT,使用Verilog HDL 语言的FFT-FFT based on Quartusii
clock
- digital clock in VHDL.
ep3c
- nios9.0下载epcsXX不能自举问题，内含补丁、例程。网友提供，但这位伟大的网友目前找不到。-nios9.0 BUG
vhdlPowerPoint
- 系统介绍VHDL语言，对VHDL的学习非常有用，欢迎大家下载~-VHDL system descr iption language, VHDL is very useful to learn, are welcome to download ~
FPGA-verilog
- 用Verilog语言编写的一些简单的FPGA入门实验，用ALTERA DE2开发板和Quartus_II软件开发环境。包括：流水灯实验、数码管显示实验-With Verilog language preparation some simple introduction experiment, with FPGA ALTERA DE2 development board and Quartus_II software development environment. Include water l
FPGA_test_frequency
- 基于FPGA的高精度测量频率的程序，里面有FIFO的子函数，代码完整-FPGA-based high-precision measurement of the frequency of the procedure, there are FIFO, Functions, code integrity
zhuantaiji
- 简单的状态机设计，功能是检测一个5位二进制序列“10010”。考虑到序列重叠的可能，有限状态机共提供8个状态（包括初始状态IDLE）。-Simple state machine design, function is to detect a 5-bit binary sequence " 10010." Taking into account the possibility of overlapping sequences, finite state machines prov
vote
- 此程序是七人表决器，代码中运用了case和IF这两种语句，可凭个人自由选用！-This program is a vote of seven, code in use of the case and the two IF statements, present their selection of individual freedom!
dds
- 基于FPGA的DDS函数信号发生器代码DDS-may cause permanent damage to the device
verilog_ams
- VERILOG ANALOG MIXED SIGNAL MODELING TUTORIAL