资源列表
pulser_16
- 脉冲发生器，周期，延迟，脉宽均可调，调节部分使用niosII内核控制，已验证可用-Pulse generator cycle, delay, pulse width adjustable
PWM_LCD
- 使用VHDL实现对LCD亮度的调节，原理是PWM脉宽调制，已验证-Use VHDL adjust LCD brightness, and the principles of the PWM pulse width modulation, Verified
verilog
- 用于黑金开发板的例程，为verilog源代码，编译正确，可直接下载至开发板中。-Routines for black gold development board for verilog source code, compile properly, can be directly downloaded to the development board.
Digital_clock11
- 基于FPGA芯片设计多功能数字钟，具有任意时刻定时闹钟，有分频器，计数器，等等模块构成-Regular alarm clock based on the FPGA chip design multifunction digital clock, any time, divider, counter modules
dianzhenxin1
- 基于FPGA芯片设计点阵显示，具有汉字显示功能，由计数器，分频器，点阵显示模块等等组成-Based FPGA chip design dot matrix display with Chinese character display function, counter, divider, dot matrix display module, etc.
detect110
- 基于FPGA芯片设计110自检测状态机，充分利用状态机实现检测110序列功能-FPGA-based chip design 110 self-test state machine, make full use of the state machine to detect 110 sequence function
V5
- xilinxFPGA v5的手册，十分详细，有利于初学者来学习xilinx的FPGA使用方法。-xilinxFPGA v5 manual is very detailed, is conducive to beginners to learn xilinx FPGA use.
final
- 一个32位的cpu设计，实际是verilog语言，只不过pudn上没有verilog的选项，希望能对你有帮助-this is a 32 bit cpu designer project,which use verilog language. Hope it could help u.
lkl
- 用门电路搭起来的13进制计数器，在7的时候有一个灯显示，初次提交，不对不处请指教-13 binary counter, gate ride up at 7 when a light display, the initial submission, please enlighten wrong not at
uart
- 这是我初学FPGA时，经过验证过的一个串口程序，大家可以下载-This is my beginner FPGA, after validation of a serial program, you can download learn
Nios-II_ref
- 介绍了niosii开发环境，以及如何使用niosii来开发FPGA-Nios II software development environment, the tools available to you, and the process for developing software.
FPGA
- fpga 设计全攻略，很好的fpga入门提高资料-the fpga design Raiders, good fpga the Getting Started improve data