资源列表
VHDL_100
- VHDL语言100例，内容很全，有电路级，行为机的设计实例-VHDL, 100 cases, the content is very wide, a circuit level, the behavior machine design example
vhdl2
- vhdl设计实例二：测试向量级波形产生，状态机实例-vhdl Design Example Two: Testing the order of waveform generation, the state machine instance
FPGA_system_design
- FPGA最小系统设计教程，内容全面-Minimum System FPGA design tutorials, comprehensive
miaobiao
- vhdl实现秒表，功能包括计时、冻结时间显示、暂停-vhdl implementation stopwatch functions, including time, freezing time display, pause
AVD
- 现代的IC芯片包含丰富的触发器，不同电路的时钟驱动源存在频率和相位的差异，因而出现了跨不同时钟区域进行异步数据传输的要求。亚稳态问题是异步数据传输过程面临的主要问题，本文提出多种跨越异步时钟边界传输数据的方法，它们包括FIFO法和脉冲展宽处理等同步方法。 -Modern IC chip contains a wealth of trigger, the clock drive source different circuit exists between the frequency and ph
sdram_control
- 基于硬件语言Verilog的一个sdram控制器的设计以及仿真-Verilog language, a hardware-based controller design and simulation sdram
MPSK-modemVHDL
- MPSK调制解调器的设计与仿真实现的文档，内附有代码-Design and Simulation of MPSK modem implementation document, containing a code
vendingmachine
- 模拟实际的自动售获机，一共分1分，2分，3分，5分几种情况，根据按下的键的不同，灯会有不同的亮法，在按下的键等于“五分”的效果时，又会跳到另一种显示状态，按下复位键后，又恢复初始状态-Simulate the actual vending machines have been a sub-divided into 1, 2, 3, 5 several cases, according to press different keys, a bright light will have a diff
serial2parallel256
- Complex Add in Vhdl with generic parameter
complex_mult
- Complex mult in vhdl
new_complex_mult
- new approach to compute complex mult with only 3 real mult
CircuitdesignwithVHDL
- Circuit design with VHDL by VOlnei A padroni