资源列表
altera-uart
- ALTERA UART sopc 软核的VHDL描述-ALTERA UART VHDL DESCRIBE
deng
- HDL verilog 电子密码锁 输入错误后有报警 输入正确后有提示-HDL Verilog electronic code lock input errors have prompted alarm input is correct
Control
- vhdl， 抢答器的一些功能，主持人可以控制4个按键，很好的课程设计-VHDL, some of the features of Responder, the host can control the four buttons, good course design
FPGA_Project_Files
- FPGA_Project_Files基于PCI控制的LED跑马灯-FPGA_Project_Files PCI-based control of the LED Marquee
FPGA
- FPGA应用开发典型实例之片上硬件乘法器的使用-The use of FPGA application development typical example of on-chip hardware multiplier
hh
- 此文件是一个Butterworth IIR滤波器的VHDL程序，此滤波器是10阶的，通带频率在2.5MHz——7.5MHz，采样频率为200MHz。此滤波性能不是很好，仅供参考。-This file is the VHDL program in a Butterworth IIR filter, this filter is 10 bands, the frequency of the passband of 2.5MHz- 7.5MHz sampling frequency is 200MHz
plot_f1
- 此程序的功能是对Quartus II软件仿真完成之后，导出的.tbl文件进行matlab画图，画出其时域图和频域图。其中待处理的.tbl文件，我将其进行人工处理，手动删除了无用信息，只剩余时间点、输入信号和输出信号。-The function of this program after the completion of the Quartus II software simulation, export tbl file matlab drawing, draw a diagram of th
Final_Vinod
- AES algorithm with 64 bits
Attachments_2012_06_28
- A2d converter in VLSI
counter
- 一個三角波產生器 適用於PWM上的使用-A triangular wave generator is suitable for PWM use
Atlys_AC97_EDK_demo
- vhld code for audio codec
chipscope-pro-software-overview
- chipscope.......demo note