资源列表
telephone
- telephone system:telephone number,area cose
FIFO_Syn
- 同步FIFO功能，verilog语言描述，通过了modelsim 6.0 仿真，Quartue综合
jishuqi
- EDA课程实验计数器 16位基本计数器 并可简易级联为48位 96位计数器-EDA course experiment the basic counter and 16-bit counter cascade of simple 48-bit counter 96
uart_tx
- 用Verilog实现通过上位机向串口发送多帧数据，并具有抗噪功能-Implementation serial port receive more frame data by software use Verilog, and has the function of the resist noise
example3
- 加/减法计数器：本程序实现的是一个加/减8进制计数器-Add/down counter: The program implementation is a plus/minus 8 binary counter
cheng1.rar
- 用VHDL实现十六位移位乘法器 才有移位相加法来实现,Use VHDL to achieve 16-bit shift multiplier shift only the sum of law to achieve
ps2_keyboard
- PS2 keyborad键盘扫描模块 可以实现FPGA的PS2通讯-PS2 keyborad keyboard scanning module can be implemented on FPGA PS2 newsletter
example3
- 加减法计数器： 本例程为加减法计数器，主要实现的加减法计数的功能。 有3个控制端口： 1、rst复位控制低电平有效； 2、en使能控制高电平有效 3、up加/减控制，高电平加法，低电平减法。-vhdl
DE2_Top
- 基于EP2C35F672Ｃ的ＥＤ２实验板自带源文件。DE2_Top，基础顶层文件，包括一些引脚设置。-ED2 based on the experimental board comes EP2C35F672C source file. DE2_Top, basic top-level documents, including some of the pin.
zl30160_pll_config_interface_model
- zl30160锁相环逻辑配置接口模块,本模块用verilog代码编写，已经过严格的电路板上的实际测试-zl30160 pll configer interface
rs_decoder_31_19_6_latest.tar
- 31.19解码器- RS code is the BCH code of multi-systerm, after a long time of development, the theory and technology of RS code has been rather mature that it can rectify burst error and random error at the same time, especially burst error. It is widel
vhdl2proc
- A structured VHDL design method