资源列表
Fibonacci_sequence
- 用MATLAB 里的XILINX BLOCKS编写, 实现Fibonacci sequence算法, 当F为0时, 输出为0 F为1时, 输出为1 当F为N 时, 输出为F的N-1 加上 F的N-2.
cpsk-vhdl
- 基于VHDL硬件描述语言，对CPSK调制的信号进行解调-VHDL hardware descr iption language based on CPSK modulated signal demodulation
adder
- adder unit designed in vhdl VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Descr iption Language.
MYCPU2.0
- 用verilog编写在FLEX10K上实现的简易CPU-used in the preparation of Verilog FLEX10K achieve simple CPU
1
- vhdl model file used for simulation and modellinf purposes
vhdl_Quick_Reference_Card
- vhdl quick reference
ADPLL
- verilog ADPLL file with testbench.v
problems123
- VHDL具有设计重用、大型设计能力、可读性强、易于编译等优点逐渐受到硬件设计者的青睐。但是，VHDL是一门语法相当严格的语言，易学性差，特别是对于刚开始接触VHDL的设计者而言，经常会因某些小细节处理不当导致综合无法通过。为此本文就其中一些比较典型的问题展开探讨，
seqdet
- 用VERILOG 语言进行的序列检测器设计，初学者多用于练习。-Sequence detector design
car_lamp
- 汽车转向灯控制电路,采用循环点亮三个指示灯指出汽车的转弯方向。-vehicle steering control circuit lights, cycle lights that lit three cars turning direction.
FIR设计实现sgh
- FIR滤波FPGA实现 ，已在仿真软件上验证实现，不是IP核，不是ip核。(FIR filter FPGA implementation, has been verified in the simulation software, not IP core, not IP core.)
HamamatsuCameralink-master
- 实现cameralink，通过xilinx 生怕日天系列实现多路decameralin(Realize cameralink, realize multi-channel decameralin through Xilinx fearful day-to-day series)