资源列表
Verilog
- 王金明版的verilog HDL的135个经典设计实例-Wang Jinming version of the Verilog HDL 135 classic design example
example2
- 状态机一般分为三种类型： Moore 型状态机：次态=f(现状，输入)，输出=f （现状）； Mealy 型状态机：次态=f(现状，输入)，输出=f （现状，输入）； 混合型状态机。 -State machine is generally divided into three types: Moore-type state machine: sub-state = f (the status quo, input), output = f (status) Mealy
example2.rar
- 状态机一般分为三种类型：Moore型、Mealy型和混合型。此程序描述了Moore型状态机的基本构成，并配以波形仿真。,State machine will generally be divided into three types: Moore-type, Mealy-type and mixed type. This procedure describes the state machine of the Moore-type basic component, and with simula
DDC
- 直接数字频率合成dds源码，cos三角函数生成代码，及测试代码，用于ddc前端测试的testbench。-direct digital frequency sysnthesis
inc
- 0到9加计数 9到0减计数
XilinxISE9.2andChinpScopePro9.2Sn
- Xilinx ISE 9.2 and ChinpScope Pro 9.2 Sn
spi
- SPI总线的RTL源代码，很好用，省掉你大量的工作量-the spi bus RTL Code
CodeVisionAVR-WinAVR
- SPI recever avr programing
prueba
- Test for VHDL just a student version
lcd
- LCD控制程序，可以很好的控制LCD的运行-LCD control program, a good control of the LCD operation
add
- 4位并联全加器的fpga实现，由4个一位全加器及一个超前进位器组成，可向上进位-Four parallel QuanJia device fpga realizing by 4 a QuanJia emulators, and a leading sensor into binary, can carry up
CPUverilog
- pic cpu source code. it is writed in the verilog source code. it can work on the 40Mhz high speed.