资源列表
sd_verilog
- 关于sd卡的控制器verilog源代码，基于wishbone的总线协议
decoder4to16
- this is a verilog code for 4 to 16 decoder
SystemVerilog
- 几个systemveriog的例子，包括8-bit up counter和divide-by-2 counter-about systemverilog
SDCard_Controller.rar
- SD卡控制器IP. 兼容SD卡协议2.0。与wishbone bus 接口，方便与其他IP连接使用。 ,SD Card Controller IP. Compatible with SD Card Agreement 2.0. With the wishbone bus interface to facilitate the use of other IP connections.
bcd27seg
- Tranfer BCD to 7 Segs
fft1024
- 1024点fft verilog hdl
Array_implementation_in_VHDL
- This code to make Array implementation in VHDL.-This is code to make Array implementation in VHDL.
SystemVerilog
- 很好的SystemVerilog例子- very good
systolic
- 实现QR_RLS算法,基于fpga 的非线性功放的dpd实现-realize QR_RLS
frame_sync
- 帧同步模块的Veriolog源码。 在ModelSim下的一个工程。有测试文件。-frame synchronization module Veriolog source. The ModelSim of a project. A test document.
carryriple
- carry riple with model sim
VHDLvsVerilog
- This document is in two parts. The first part takes an unbiased view of VHDL and Verilog by comparing their similarities and contrasting their differences. The second part contains a worked example of a model that computes the Greatest Common Divisor