资源列表
frequency-meter
- 开发环境是quartus ii，是学校的一个FPGA实验，计算一个信号的频率，这个是我做得最好的一个作品，调试成功。压缩包里包含题目要求以及我做好的模块。-Development environment is quartus ii, an FPGA experimental school, calculate the frequency of a signal, this is I' m doing the best work, debugging success. The compres
write1
- 串行接口发送，通过绑定DE2上的拨码开关，然后通过RS232接口传送到pc上，可通过串口调试大师接收数据-Serial interface to send, through binding DE2 DIP switch, and then transmitted via the RS232 interface to the pc, can receive data through the serial debug master
DDS
- DDS正弦波发生模块 基于verilog语言实现 在cycloneii系列FPGA上经过验证 频率步进1khz 共有256个点-The DDS sine wave module based on verilog language achieve in cycloneii series FPGA proven frequency stepping 1khz 256 points
I2C
- 基于verilog的I2C代码，包含master和slave两个模块-Verilog-based I2C code that contains the master and slave two modules
RISC_CPU
- 基于verilog的risccpu实现，只有一个指令，对于了解risccpu的工作原理很有帮助。-Based on verilog of risccpu, only one instruction, helpful for understand risccpu works.
SOPC_watch
- 基于ALtrafpga的niosii内核verilog语言实现的可编程电子钟，需要外接lcd屏幕-Programmable electronic clock, based on the the ALtrafpga the kernel niosii verilog language to achieve an external lcd screen
27072158834900
- 使用FPGA进行北极光设计，非常漂亮的小制作。使用VERILOG HDL语言-Using FPGA design northern lights, very nice production. VERILOG HDL languages
signal_generator
- 信号发生器的FPGA实现，能输出正弦信号，方波信号，三角波信号-FPGA implementation of the signal generator can output a sinusoidal signal, square wave signal and triangular wave signals
AM
- FPGA简单实现幅度调制，所使用软件为ISE，仿真工具是modelsim-FPGA realization of a simple amplitude modulation, the use of software for the ISE, and simulation tools is modelsim
verilog
- 实现1602的显示，实
dac7621
- dac7621数模转换驱动，使用verilog语言写的。-dac7621 digital to analog conversion drive
ads831
- ADS831模数转换驱动，使用verilog语言写的。-ADS831 analog-digital conversion drive, write verilog language.