资源列表
most_latest.tar
- MOST总线是被广泛被应用于车载媒体数据传输的总线，本源码采用verilog语言编写了其控制器，其特点是具有很高的用户可定制性。-MOST bus is to be widely used in car media data transmission bus, the source verilog language of its controller, which is characterized by high user customization.
simple_spi_latest.tar
- - 与摩托罗拉的SPI规格兼容 - 增强摩托罗拉MC68HC11串行外设接口 - 4项深读FIFO - 4项深写入FIFO - 中断后1代，2，3或4个转移字节 - 8位WISHBONE RevB.3经典界面 - 经营的输入时钟频率范围广泛 - 静态同步设计 - 完全可合成 - 130LUTs在Spartan-II，230在ACEX LCELLs的-- Compatible with Motorola s SPI specifications - Enhanced Motorola MC6
xiaqdq
- 基于FPGA的4路抢答器VHDL源代码，完整工程-4-way Responder based on FPGA VHDL source code
bjq
- 基于FPGA的半加器，完整工程及代码，已测试-FPGA-based half-adder, full engineering and code
cfq
- 基于fpga的乘法器设计，完整代码及工程-Fpga-based multiplier design, the complete code and engineering
fpq
- 基于fpga的分频器设计，完整代码及工程-Fpga-based crossover design, the complete code and engineering
ipfp
- 基于fpga的分频器设计，利用ip核做的，完整工程及代码-Fpga-based crossover design, using the ip nuclear, complete engineering and code
crc_tool
- 用c编写的自动生成并行crc处理的verilog代码的工具-Automatically generate the verilog code to parallel crc processing tools written with c
prbs
- 高速并行数据伪随机化模块，包括发送侧的随机化和接收侧的去随机化，以及测试模块-High-speed parallel pseudo-random data modules, including randomized and receive side of sending side to randomization, and the test module
m_seq
- 用VHDL代码编写的m序列发生器，包含发生器和测试用例模块-M sequence generator written in VHDL code, including the generator and the test case module
agc
- 无线通信中接收侧自动增益控制模块的vhdl代码实现-Receive side of the AGC module vhdl code for wireless communications
cic-1
- cic滤波器2倍抽取verilog代码及testch-cic filter decimation verilog code and testch