资源列表
ADPCMDecoder
- ADPCM decoder working on Xilinx ISE 12.2 code includes core ICON ILA VIO test on chipscope
myCounter_top
- A simple Counter code inculdes core of ICON VIO ILA, works on ISE 12.2 and chipscope to test the board.
Logicos
- Is a Simple andOr, xor, sr circuit on Verilog and his testBench
pruebacont
- Param Counter Verilog
VHDL_coding
- Powerpoint slides about VHDL coding which teaches in class, inculdes many lesson and also parctice.The ppt file is for learners who want to begin with VHDL.
cun
- 通过fpga使总线上的数据存储到spi进行读写-Through the fpga to store data on the bus to read and write spi
djdplj
- 运用等精度测量原理,结合单片机技术设计了一种数字式频率计,由干采用了屏蔽驱动电路及数字均值滤波等技术措施,因而能在较宽的频率范围和幅度范围内对频率、周期、脉宽、占空比等参数进行测量并可通过调整闸门时间预置测量精度。-The use of other precision measuring principle in combination with single chip technology to design a digital frequency meter, shielded from t
VHDL-djdplj
- 基于VHDL语言的十进制等精度频率计的设计，采用VHDL语言，运用自顶向下的设计思想， 将系统按功能逐层分割的层次化设计方法，使用Quartus8.0开发环境，实现了频率计的设计。-VHDL language based on the decimal precision frequency meter, etc. The design, using VHDL language, the use of top-down design, the system is divided by func
clock
- Real simply clock on verilog
Simply3verilogexample
- Sympli 3 verilog example
Bibus
- bibus verilog example
vme_sv
- voice modulation engine, a DSP processor with test bench written in SystemVerilog