资源列表
seriall2parallel
- its code for converting serial to parallel processing data
bancada1
- QUARTUS EXAMPLE EXPERIENCE
ula2
- QUARTUS EXPERIMENT 3
tutorialFPT101
- FPGA QUARTUS TUTORIAL HOW TO USE QUARTUS -FPGA QUARTUS TUTORIAL HOW TO USE QUARTUS
exp1
- QUARTUS EXPERIMENT EXAMPLE
ml50x_schematics
- Xilinx ML505/6 Board Schematics
vhdlcodesss
- i attached the vhdl codings-i attached the vhdl codings..........
attachments_2010_04_07
- Stepper motor speed controller
11
- Verilog HDL程序设计与实践，从入门到提高，必备的资料-Verilog HDL program design and practice, from entry to the improvement of the information necessary
design
- 详细讲述了FPGA仿真与设计环境的建立，以及如何使用IP核，如何烧录文件-Detail the FPGA simulation and design environment to establish, and how to use IP cores, how to burn files
switch
- 该模块是一个基于verilog的脉冲触发高低电平保持的模块，同时包含了消抖的功能。 主要是针对现今许多开发板上开关是弹簧式的手按下去为低电平，手一松就变成了高电平。只要按一次松开后，模块就能自动输出一个低电平。（板子上的开关正常情况为高电平） 同时消抖部分在输入clk为50Mhz的时候可以延迟21ms来判断是否为开关按下-The module is based on verilog pulsed high-low to keep the trigger module includes b
multiplier_csa
- 8 bit Multiplier, CSA type