资源列表
S3_WAVE
- 这是一个波形发生程序 运行环境是quartus2 已通过编译-The code is to generate a wave welecome to download!
mulhoulai
- 这是一个乘法器的Verilog实现，这是仿真AMR处理器核中的乘法器开发的。挺不错的。-It is a multiplier using the Verilog.
RS232_ysd
- 串口接口控制器参考设计VHDL代码,方便开发FPGA人员进行串口的开发，是一个不错的源码解压安装后可在quartus里例化使用-Serial interface controller reference design VHDL code, facilitate the development of FPGA serial port staff development, is a good source decompression after installation in case of use
DS18B20_ysd
- 在quartusII下开发的DS12B20_vsd的verilog程序，方便大家的学习。-Developed under the quartusII DS12B20_vsd the verilog program to facilitate everyone' s learning.
led_ysd
- 在quartusII下开发的八段码的verilog程序，方便大家的学习-In eight out quartusII developed under the code verilog program, we facilitate the learning
light_ysd
- 在quartusII下开发的流水灯的verilog程序，同时程序里还有分频的程序，方便大家的学习-Developed under the water in the quartusII light verilog program, and the program divided the program in there, we facilitate the learning
VGA_ysd
- vga接口控制器参考设计VHDL代码,方便开发FPGA人员进行vga的开发，是一个不错的源码解压安装后可在quartus里例化使用-vga interface controller reference design for VHDL code, and facilitate the development of FPGA vga staff development, is a good source installed after decompression in the case of usi
lcd12864_EP3C10
- 在quartusII下开发的lcd12864的verilog程序，方便大家的学习。本程序基于EP3C10T144芯片-Developed under the quartusII lcd12864 the verilog program to facilitate everyone' s learning. The program is based on EP3C10T144 chip
ADCINT
- EDA的ADC0809的应用,使用VHDL编码 实现模数转换功能,方法简单易行.-The ADC0809 EDA applications, the use of VHDL Coding analog-digital conversion function is simple and easy.
adder
- 一位全加器,使用绘图方式,将2个半加器制成符号,供全加器调用,组合成全加器,方法简单易行,通过验证.-A full adder, using the drawing method will be made of two half adder symbol calls for the full adder, adder combination of sake, the method is simple and verified.
CNT4
- 4进制加法计数器,实现简单的4进制计数功能, 有进位输出,清零复位的功能,简单易行.-4 binary counter addition, the 4 simple binary counting function, carry out, clear reset function, simple.
COUNTER32B
- 32位移位寄存器,实现具体右移功能的32为寄存器,结构简单,通过时序验证-32-bit shift register 32 functions to achieve specific right to register, simple structure, through the timing verification