资源列表
uart
- UART模块的verilog代码，经过测试，能够实现正常的接收和发送功能。-Verilog code for UART module has been tested, it is able to achieve normal receive and transmit functions.
gps_code_gene
- GPS信号C/A码生成器，能够实现gps接收机中c/a码的剥离。-GPS signal C/A code generator is able to achieve a GPS receiver C/code peeled.
doorlock.rar
- 门锁 状态机 verilog 适用于digilent NEXYS2开发板,doorlock state machine verilog applied to digilent NEXYS2 board
uC_interface
- IIC总线微控制器的接口RTL代码（verilog）-the verilog code of IIC Uc_interface
assg-2-2-code-converter
- CODE CONVERTER IN VHLD ,Binary to Gray using structural modelling of XOR Gate
assg-8-(barrel-shifter)-final
- Barrel shifter IN VHLD , using structural modelling
assg-5-(serial-bit-adder)
- 4 bit adder using four full adder’s structural modeling style
miaobiao
- 用VHDL语言实现对FPGA的程序编写，实现秒表功能。-Using VHDL FPGA program written stopwatch function.
jiafaqi
- 用VHDL语言实现对FPGA的程序编写，实现加法器功能。-FPGA program written using VHDL adder function.
liushuideng
- 应用VHDL语言实现FPGA的编程，实现流水灯功能。-Application VHDL language for FPGA programming, light water feature.
anjianshumaguan
- 应用VHDL语言实现对FPGA的程序编写，实现按键数码管的功能。-Using VHDL language to write FPGA procedures to achieve the key function of the digital tube.
assg-9-1-(lift-controller)
- Lift Controller in vhdl using process statement and state disgram