资源列表
lfsr-counter
- descr iption for LFSR counter
memories-dual-port
- descr iption for memory dual port
encoder-8b10b
- 可以实现8b10b编码，verilog源程序，经过测试-8b10b Encoder
sourcefiles-for-chip-scope-(serial-type-IDEA)
- this code is for IDEA(international data encryption algorithm)
zedboard
- 关于xilinx最新出来的开发板zedboard的一些资料-Information about the xilinx Latest the development board zedboard out some
another
- 这是一个用数码管显示的verilog语言描述的数字秒表，且引脚已经分配完毕，基于DE2，可直接下载到板子上使用-This is a digital stopwatch with digital display verilog language described, and the pins have been fully allocated, based DE2, can be directly downloaded to the board
FPGA-Communication-Framework-.tar
- 这是来自开源网站OpenCores的程序，版权归作者所有，仅供学习交流。一个上位机软件源程序，和一个FPGA硬件核的源程序（<600slices），上位机软件可以通过UDP/IP连通FPGA实现通信。-This is from the open source the website OpenCores the program belongs to the author, only learning exchanges. A host computer software source cod
vhdl_demo2
- 设计PCM30基群帧同步电路1．输入码流DATA，速率为2.04Mb/S；每帧256bit，其中前8bit为帧同步码；偶数帧的帧同步码为10011011，奇数帧的帧同步码为110XXXXX（X为任意值）。 2．系统初始状态为失步态，失步信号FLOSS输出低电平，电路在输入码流里逐比特搜寻同步码，当搜寻到第一个偶帧同步码后，电路转为逐帧搜寻，当连续三帧均正确地搜寻到同步码后，系统状态转为同步态，失步信号输出高电平；否则电路重新进入逐比特搜寻状态。 3．系统处于同步态后，当连续四帧检出的同步
true_dual_port_ram_single_clock
- Quartus II VHDL Template. True Dual-Port RAM with dual clock.
true_dual_port_ram_dual_clock
- Quartus II VHDL Template True Dual-Port RAM with dual clock
single_port_ram_with_init
- Single-port RAM with single read/write address and initial contents
simple_dual_port_ram_dual_clock
- Simple Dual-Port RAM with different read/write addresses and different read/write clock