资源列表
ddr_verilog_xilinx
- 该程序是在xilinx的FPGA上实现DDR_SDRAM接口，程序是用verylog语言写的-that the procedure was in Xilinx FPGA to achieve DDR_SDRAM interface, procedures used to write the language verylog
ddr_verilog_xilinx
- DDR_verilog_xilinx 原语-Primitive DDR_verilog_xilinx
vhdlExamples
- VHDL 设计模块 例程 若干个 -several examples of VHDL design~~~~~~~~~~~
mux16
- mux 乘法器 verilog ise xilinx-the mux multiplier Verilog ise xilinx
NumClock
- 基于Altera公司系列FPGA(Cyclone EP1C3T144C8)、Verilog HDL、MAX7219数码管显示芯片、4X4矩阵键盘、TDA2822功放芯片及扬声器等实现了《电子线路设计• 测试• 实验》课程中多功能数字钟实验所要求的所有功能和其它一些扩展功能。包括：基本功能——以数字形式显示时、分、秒的时间，小时计数器为同步24进制，可手动校时、校分；扩展功能——仿广播电台正点报时，任意时刻闹钟（选做），自动报整点时数（选做）；其它扩展功能——显示年月日（能处理
VGA_Controller
- 这个文件简直太好了，是个ip，费了好大的力气弄好的，可以挂在avalon总线上，用dma的方式将数据弄处理放在vga上进行显示。-This file is simply too good to be a ip, take a great effort things right, you can hang in the avalon bus, with the way the data get dma handle on the vga on the display.
ISE8.1_loopback
- 硬件平台为Xilinx Spartan3e，编译软件为ISE8.1，实现了九针com口通信，键盘输入回显，switch控制LED功能。-hardware platform for Xilinx Spartan3e, compile software ISE8.1. achieved nine needles com port communication, a return to the keyboard input, LED control switch function.
arith_lib_fdl
- A comprehensive library of arithmetic units written in synthesizable VHDL code has been developed.
code-pour-decim-poly
- this code is for a decimation filter with polyphase structure , so the original filter is decomposed by 5 filters which is the decimation factor in that case and each of them is selected each Fs/5
fdivision
- 简单的分频器的VERILOG设计，带测试代码。初学者适用。-Simple prescaler VERILOG of design, with the test code. For beginners.
dds_test
- 这是用c8051f020单片机驱动ad9854产生波形的测试程序-This is c8051f020 chip driver ad9854 waveform generated test program
multt
- 该程序实现了一个16*16的乘法器，可以用作设计乘法器参考-The program implements a 16* 16 multiplier, multiplier design can be used as reference