资源列表
i2s_master_slave_vhdl
- i2s串行线广泛用于音频通信中,这里包括了master和slave的代码.-i2s serial lines widely used in audio communication, here including the master and slave codes.
shumaguan-Verilog
- 简单的数码管电路设计实现代码 verilog-Simple digital circuit design implementation code verilog
chengfaqi
- 一个乘法器，比较简单，但也是自己认真写的，上传上来了-hahahhahhahha
LED
- 在实验箱的LED矩阵实现"武汉商业服务学院 信息工程系"的显示 要求:1.设计字库 2.表态显示逐个字切换显示 3.最终实现 流水显示 -In the experimental realization of the LED matrix box " Wuhan Commercial Service College of Information Engineering," the display requirements: 1. Designed font 2
LCD_timer_clock
- 液晶定时器时钟，通过定时器控制时间显示在lcd上-LCD timer clock, a timer control on the time display in the lcd
test_iic
- modelsim 下对iic进行仿真 包含iic时序说明-modelsim simulation under iic
lcd1602
- 08 1602LCD随机模拟显示乘法口诀08 1602LCD随机模拟显示乘法口诀-08 1602LCD stochastic simulation shows the multiplication formulas 08 1602LCD stochastic simulation shows the multiplication formulas
EPM7128TMS320LF2407A
- emp7128在电平转换中的应用 希望大家下载，必定收益
mux16_1
- 高速并行，有符号16选一的MUX，完整的VERILOG功能模块和测试平台-High-speed parallel, 16 elections have signed one MUX, a complete functional module and test platform VERILOG
freq_4
- 4分频时钟，同步，带清零功能。可用于时钟分频设计-4 divided clock, synchronization, with clear function. Can be used for clock divider design
EDA
- eda实训 VHDL语言编写 多种实训课题-eda
Part-
- data transfer from one multiport ram top other multi port ram. it is a system generator compatible bile