资源列表
Project
- Arithmatic logic unit
PL_FSK2
- 基于altera公司的quartus软件做的2FSK解调-The doing altera quartus software 2FSK demodulation
ADDER
- VHDL语言的带控制端口的加法器，实现加法运算。-VHDL language, with a control port of the adder to achieve addition operation.
PWM_IP
- 电源控制系统的PWM核,测试可用...FPGA-Power IP,PWM
B2
- This a vhdl program-This is a vhdl program..
1_ADDER
- ADD加法运算可实现从0到10的加法运算-ADD addition can be realized 0 to 10 of the addition operation
telecom
- atm通信协议验证平台，采用vmm采用vmm采用v-atm communication protocol validation platform, vmm
投币充电仪
- 基于FPGA的投币式充电仪，可以完成按键输入、倒计时、清零等功能。
verilog-midi-reader-master
- MIDI file parser that converts song and lyric data to Verilog ROM format for use on an FPGA
FIR.ip
- zedboard 开发板学习资料 FIR滤波器的 代码 -code to implement the FIR function on zedboard
bmp
- Quick BMP-Test for CY7C68013A-USb device. Ready to run program for FPGA.
clock
- 用VHDL编写的电子钟，可以显示时间，调节时，分，秒；有整点报时功能。-Prepared using VHDL clock can display time, adjust hours, minutes, seconds a whole hour.