资源列表
UARTipcore
- 这是一个关于UART的IP核，用VHDL写的。经过本人的鉴证，非常实用并且写的非常好。-This is one of the IP core on the UART, using VHDL written. After my verification, very practical and very well written.
eeprom
- EEPROM INTERFACING TO 8051
uart_ise_vhdl
- fpga里实现 uart 经典 vhdl语言写的 ise工程文件-fpga implementation in vhdl language classic uart of ise project file
testbench
- 介绍如何编写verilog的仿真程序，很适合初学者-How to write verilog simulation program, it is suitable for beginners
test
- 一个进位计数器的简单verlag实现，仿真无误-A simple binary counter verlag achieved, the simulation is correct ... ...
wtb
- 简单实现位同步，适合初学者译码成功！请验收-very good，please trust me!!!!!!
VerilogHDL_advanced_digital_design_code_Ch4
- Verilog HDL 高级数字设计源码 _chapter4
ycrcb2rgb
- 用verilog实现ycrcb至rgb的色彩空间格式转换，可综合-ycrcb to rgb colour space convey
s3esk_picoblaze_dac_control
- picoblaze DAC control spartan 3e
blockram
- 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
Bai1.5
- Code example for verilog FPGA
UART
- 用硬件描述语言实现的uart的IPcore，有详细的注释和测试文件-Hardware descr iption language of the H.264 encoder, detailed notes and test files