资源列表
8080
- EPM1270和单片机的8080通讯接口，适合单片机与CPLD之间的高速通讯，verilog语言，QuartusII环境
MOTO
- 步进电机的马达定位控制 vhdl 源码 内容包括 控制正反转，复位开关，设定的度数的二进制代码。-Motor stepper motor positioning control the vhdl source content control Reversible, reset switch, set the degree of binary code.
Multiplier
- BJ-EPM240V2实验例程以及说明文档实验之五乘法器设计-BJ-EPM240V2 experimental test routines as well as documentation of the five multiplier design
communications_1
- 用vhdl代码描述的通信系统仿真程序。包括信源（20位m序列），crc编码（采用串行算法），加噪（用22位m序列产生稀疏的1，然后和编码后的数据异或）。-Vhdl code with the simulation program described in the communication system. Including the source (20 m sequence), crc code (using the serial algorithm), noise (with 22 m se
Sin_wave
- sin波形信号发生起的程序 VHDL语言描述 QUartus
dac7512
- 实现A/D转换,给定输入，观察输出电压，VHDL程序。-Implement A/D conversion，Given input, observe the output voltage, VHDL program.
ad9854fpga测试程序
- 基于fpga和ad9854的dds发生器，包含测试程序
74hc4017
- 实现的是扭环形十进制计数器，用verilog HDL 语言，在Actel公司提供的LiberoFPGA开发环境下实现，代码经过验证，可在ModelSim中仿真 -Ring is twisted to achieve a decimal counter, using verilog HDL language, Actel offers the LiberoFPGA development environment, the code is validated, the simulation in t
Alarm
- The aim this project is to implement the functionality of a digital alarm clock on a FPGA. As soon as the FPGA is switched on, the clock starts. The alarm can be set using the dip-switches provided on the FPGA board. This is indicated through the LED
OV7670initial
- ov7670硬件初始化代码，运行在alteral cyclone 2 fpga上-the hardware initializition of ov7670,running at cyclone 2 fpga platform
PWM
- PWM Source Code in VHDL For FPGA Devices
chenyu--chengxu
- 用verilog语言编写的串口通信程序,可以作为一个地址选择控制器使用，实现和不同的串口设备通信-Using verilog language serial communication program, can be used as an address selection controller, implementation and communication of different serial devices