资源列表
ISE_lab16
- 使用VHDL语言设计数字钟。 数字钟由晶振、分频器、计时器、译码器、显示器等组成-Digital clock design using the VHDL language. Digital clock from the crystal oscillator, frequency divider, timer, decoder, display and other components
ise_lab16_dcm
- 数字时钟设计 excd-1开发板 适合初学者学习-excd-1 DCM
pll_self_rst
- 用于检测ALTERA FPGA PLL应用中出现的假锁定问题(Used to detect false lock problems in ALTERA FPGA PLL applications)
FinalCPU
- 用VHDL语言编写的简单CPU程序,实现了加减乘除和移位功能。-a simple CPU program writen by VHDL language , it realizes the add, subtract, multiply ，divide and shift function.
elvator_control_base_on_fpga
- 这是一个使用VHDL语言设计的电梯控制程序，里面还有仿真时序图。
example
- 一个电子秒表，最大显示59.99,具有暂停和reset功能-An electronic stopwatch, the maximum display 59.99, with a pause and reset functions
elec_lock
- 电子钟源文件，显示时分秒星期，按相应按键，可以对时分星期加1调整时间-钟源electronic documents to show the weeks when the minutes and seconds, press the corresponding button, you can adjust the hours of time plus 1 week
EDAjiaotongd2
- 此文档包含基于CPLD芯片的交通灯设计方案和其程序-This document includes the traffic lights based on CPLD chip design and its procedures
PS2_PCM_VGA
- ps2信号输入经解码通过vga显示输出，能显示0~9任意一个数字在屏幕。-ps2 signal input by the decoder through the vga display output, 0 to 9, any number can display on the screen.
ISE_lab16
- 简易数字频率计，可以运行。可用ise10.0以上版本打开-Simple digital frequency meter, you can run. Available ise10.0 version open
Attachments_2012_06_19
- verilog basic materials-verilog basic materials
chengxu
- EDA实验程序实现8位全加器，999计数器数码管显示以及频率计数器显示的源程序。。。以经过测试。-EDA experimental procedures to achieve 8-bit full adder, counter 999 and frequency counter digital display shows the source. . . To be tested.