资源列表
eda
- 来自某名牌大学电子实验室的eda指导教程，主要介绍了maxplus2，适合初学者
Chapter-6
- 用Verilog编写的SPI协议包括了最基本的协议和功能，并通过测试。本SPI是主。-SPI using Verilog written agreement includes the most basic protocols and functions, and passing a test. The SPI is the main.
altera_up_avalon_irda
- Altera大学计划的红外通讯IP，avalon接口-Altera University Program of the infrared communication IP, avalon interface
FPGA_CPL
- FPGA_CPLD在线实时自主可重构系统技术及其在软测量中的应用-FPGA_CPLD line real-time self-reconfigurable system technology and its application in soft sensor
quartus-II
- 用Quartus II实现答辩计时器设置，大致功能有时间显示，倒计时提醒，暂停键等。-Quartus II realized by the respondent timer settings, roughly the time display function, countdown reminder, the pause button and so on.
实验11 电容触摸按键实验
- 电容触摸屏实验 采用触摸屏 基于stm32 实现实时控制(Capacitive touch screen experiment, touch screen, real-time control based on stm32)
LCD1602-fpga-verilog
- 功能：LCD1602显示屏显示PS2键盘的键值。用verilog编写。-LCD1602 display shows the the PS2 keyboard keys verilog
shujujiance
- 单进程Mealy型数据监测。实现100101的数据监测，可实现多次组合监测，更改移植方便简单。-Mealy-type single-process data monitoring. Achieve 100,101 data monitoring, enabling multiple portfolio monitoring, change transplantation convenient and simple.
Fireandpassword
- Fire&password数字系统实验，实现密码锁，有报警的显示
dividend4
- 本设计是一个八位被除数除以四位除数，得到不超过四位的商的整数除法器。被除数、除数、商和余数都是无符号整数。-The design is an eight dividend divided by the divisor of four, to be not more than 4 business integer divider. Dividend, divisor, and remainder are unsigned integers.
rentifanyingshijian
- 测试人体视觉的反应时间，可以作为vhdl编程的练习之用，也可以更进一步的开发成为具有商业价值的产品，这里面只是能够实现测试人体视觉反应时间的基本功能的程序
stopwatch
- 用Verilog编写的秒表，可以实现计时、复位、暂停等功能。-stopwatch using Verilog language