资源列表
Serial
- 串口的设计思路和需要注意的问题 包括.v 文件-include serial.v file
VHDL-ASK
- 基于VHSL语言的的ASK调制与解调，用max+plus进行了仿真及分析-VHSL language based on the ASK modulation and demodulation, with max+ plus simulation and analysis
0514
- 16位4*4寄存器组 可以用于模拟主机系统设计时使用-16B reg
tlc549
- 芯片的详细解释，合理运用芯片，主要用于数模转换-Chip detailed explanation of the rational use of chips, mainly used for digital-analog conversion
VHDL380examples
- 对初学vhdl的人有很多帮助，很有用的程序，很实用-Vhdl for beginners who have a lot of help, very useful program, it is useful
qdq
- 基于ＦＰＧＡ的多路抢答器，采用Ｖｅｒｉｌｏｇ语言编写-FPGA-based multi-Responder, using Verilog language
fulladder
- simulation full adder using vhdl-simulation full adder using vhdl
e1framerdeframer_latest
- 实现E1信号的成帧、CRC校验功能，双向通信，双工工作，实际检验通过-E1 signal to achieve a framing, CRC checking function, two-way communication, duplex work, the actual test by
miaobiao
- 秒表实验verilog代码，我已经调试好。希望供大家学习使用。-clock using counter code of verilog HDL.I debug it right
moore
- moore状态机实验verilog代码，我已经调试好。希望供大家学习使用。-moore state machine code of verilog HDL.Debug it right.
BEE
- 蜂鸣器实验verilog代码，我已经调试好。希望供大家学习使用。-Verilog HDL experiment code for bee. Debug it right.
div
- VERILOG除法器，已经调试好。大家可以参照学习.-sub-divided function,I have debug it right.It is helpful to you