资源列表
shuokongfenpin
- 数控分频器。EDA实验设计。有详细的操作不瘦-It s important foe you!
CoveragePkg
- osvvm coverage packages that is helpful for vhdl verification
gongchengsheji-477
- 基于logmap算法的vhdl的实现。 通信系统的log—map算法数字vhdl的实现-logmap algorithm based on the achievement of VHDL. The communication system log-map algorithm to achieve the number of VHDL
ps2_keyboard
- vhdl for ps2 keyword vhdl for ps2 keyword -vhdl for ps2 keywordvhdl for ps2 keyword
DigitalFilter
- 由VHDL写的多数决定的数字滤波器！QuartusII5.0的工程文件,编译通过！
FPGA_SDRAM
- FPGA对SDRAM的控制操作源码,用VERILOG硬件描述语言编写,包含的文件一共有:hostcont.v,inc.h,pinouts.ucf,sdram.v,top.v,tst_inc.h-Control of operation of the SDRAM FPGA source code, using VERILOG hardware descr iption language, the file contains a total of: hostcont.v, inc.h, pinout
clock
- FPGA的时钟设计,源代码,很有参考价值,希望对学习FPGA设计的朋友有参考意义.-FPGA clock design, source code, a good reference, would like to learn FPGA reference design meaning friends.
Moore_1001
- it is a moorey model s vhdl code which was implemented and run in altera Quarts - II
multichannel-selector
- 本程序实现了二选一多路选择器的硬件功能，采用VHDL语言编写而成。-This program implements a second election multiplexer hardware function, written in VHDL language.
Comparators_16B
- verilog 实现 优化的16位比较器 可以输出大于，小于，等于。模块化设计，可扩展为32位-Verilog achieve optimization of 16 compared with the output can be greater than, less than, equal to. Modular design, which can be expanded to 32
calculator
- 用VHDL编写的计算器，能实现简单的加减乘除四则运算