资源列表
seg
- 用verilog语言实现数码管控制工作，有问题可以qq咨询，516998649-use the verilog language to drive the seg
VHDL
- VHDL语法入门 轻松掌握VHDL的应用技巧-Introduction to VHDL grammar skills to master the application of VHDL
sdram_yadmc.tar
- /* * Yet Another Dynamic Memory Controller * Copyright (C) 2008 Sebastien Bourdeauducq - http://lekernel.net * This file is part of Milkymist. * * Milkymist is free software you can redistribute it and/or modify it * under the terms
PWM
- verilog pwm to control servo motor on quartus, with microprocessor generated from sopc and connected with sram-verilog pwm to control servo motor on quartus
vhdl-code-for-sine-wave-generator
- it is a simple code in vhdl for sine wave generator. the test bench code is also provided in ths code
vhdl-for-bluetooth
- bluetooth source code using soc and avr. the signal between soc and avr needs a basic rule in order to flow the signal
DE2_Top
- 这是一个基于DE2平台的工程，适合于初学者学习DE2开发平台的很好的工程，是用Verilog语言编写的
digital-clock
- 通过对单片机进行控制，实现数字钟定时的功能-Controlled by the microcontroller, digital clock timer function
DE2_Top
- Verilog代码，适合于初学者进行学习，是基于DE2平台的代码。
yimazhenque
- 47译码器器的verilog源代码,经过编译仿真的，绝对真确，对初学者很有帮助-47 decoder for verilog source code, compiled simulation, absolute authenticity, helpful for beginners
Half-Adder
- This is an example to implement an Half-adder for xilinx FPGA
Half-Adder
- xilinx ISE平台提供1位半加法器，模块随模拟提供(Half- adder 1- bit design implemented in ISE XIlinx Design Suite. Module in VHDL language)