资源列表
src
- 实现VERILOG音乐播放器功能，但是不能快进，能显示其歌词。 希望有帮助-Realize the VERILOG music player functions, but can t fast forward, to show its lyrics. Hope to have help
anylist-exam
- 任意模计数器FPGA程序代码设计，可实现模1000以内的任意模，更改参数可提高范围-Any mold counter FPGA code design, model 1000 can be achieved within any mode, change the parameters can increase the range
add_full_n
- 该程序实现的是n位全加器，首先用与非门实现一位全家器，最后实现n位的全加器。-the program is to achieve the n-bit full adder, first using the door with non-realization of a family - and finally realize the full n-bit adder.
MSP430UART
- MSP430单片机 串口UART实验测试程序-MSP430 UART
LDR
- This a LDR project. -This is a LDR project.
ps2_soc2
- PS2的源代码VHDL语言实现，可以和计算机直接连接．做鼠标键盘接口．-PS2 source VHDL, and can be connected directly to the computer. So the mouse, keyboard interface.
register file generation
- the zip file consist of the verilog code which generate the 32 bit reg file so that u can read and write the data into them
rs_1.rar
- rs触发器的设计，是用vhdl实现的，欢迎下载。,rs flip-flop design is achieved using vhdl.
cordicFSK
- Frequency shift keying in XIlinx system generator
基于CPLD-FPGA的半整数分频器的设计
- 基于CPLD-FPGA的半整数分频器的设计，用于设计EDA-based CPLD-half FPGA integer dividers in the design, design for EDA
lift
- 用vhdl编写的一个简单的电梯程序，可以实现电梯功能-Vhdl prepared with a simple lift procedure, can achieve lift function
examples
- Verilog HDL 程序设计教程；王金明-Verilog HDL programming tutorials