资源列表
bist
- this the good program for math-this is the good program for math
CC2530UART1Test
- 飞比开发板CC2530 串口程序 UART1Test （zigbee协议）-CC2530 development board to fly than the serial program UART1Test (zigbee protocol)
RamFifoVHDL
- Ram Fifo Core VHDL file
DDS_sinwave
- 基于FPGA对DDS芯片的仿真。能产生10M以上正弦波。并且波形不失真。-Simulation of DDS chip based on FPGA. Can produce more than 10M sine wave. And the waveform is not distorted.
vhdl3
- CAT1025是基于微控制器系统的存储器和电源监控的完全解决方案。它们利用低功耗CMOS技术将2kbit的串行EEPROM存储器和带掉电保护的系统电源监控电路集成在一起。存储器采用400kHz的I2C总线接口。我们将数据通过I2C总线的写操作送到EEPROM里面，然后，再通过I2C总线的读操作将其读出。-CAT1025 is based on the micro-controller system memory and power monitoring of complete solution.
PLL
- Phase locked loop(PLL) Verilog HDL code
memories-dual-port
- descr iption for memory dual port
i2c
- I2C是一种工程应用非常广的协议 在FPGA中的实现
traffic
- vhdl实现交通灯的控制，具有行人优先原则，最大程度的实时监控-vhdl achieve control of traffic lights, with pedestrian priority principle, the greatest degree of real-time monitoring
CANoe_Beispiel
- CAN Controller code VHDL
basics
- 函数化编程思想的应用。与微软F#类似。定义变量函数，利用已定义的进行编程实现功能
parity_generator
- parity generator Parity bits are extra signals which are added to a data word to enable error checking. There are two types of Parity - even and odd. An even parity generator will produce a logic 1 at its output if the data word contains an odd num