资源列表
source-code
- 关于算法的vhdl程序，没有错误，可以使用-Vhdl program for the algorithm, there are no errors, you can use
examples
- Verilong 经典例子 王金明：《Verilog HDL 程序设计教程》-Wang Jinming Verilong classic example: " Verilog HDL Design Tutorial"
SampleEngine
- source code of sample program
DE2_system_Top
- DE2_system_Top ALTERA的DE2开发板卡的资料-DE2_system_Top ALTERA DE2 board
license
- 我搜集的比较全 QII9的license-FULL VERSION OF QII9 LICENSE
m1_core.tar
- 一个小巧的mips处理器，verilog写的，大家可以-A small mips processor, verilog written, we can see
dig_pll
- 一个简易的数字锁相环，可以产生一个与输入同频同相的输出时钟-A simple digital PLL can generate an input in phase with the same frequency output clock
anymode
- 任意模计数FPGA程序代码设计，可以输入任意模值，并由数码管显示计数，-Count any FPGA code design mode, you can enter any model values by digital display counts,
opcode
- 该程序为基于Verilog实现的计算程序。-The program for the calculation procedure based on Verilog implementation.
clock
- 一个简单的FPGA时钟，里面有PDF说明~-A simple clock sample. There exists a PDF statement files in it. If there exists any problem please contact me.
VerilogQuickRef
- Verilog Quick Reference
vhdl
- 10个有关于vhdl例子的程序代码，就是那种带有程序注释的那种-10 on vhdl examples of program code, that is the kind of program notes with the kind of! ! !