资源列表
MPPT_PV_12V_FPGA5
- 基于fpga的mppt（最大功率跟踪）无差拍设计-Fpga-based mppt deadbeat designs. . .
FIFO
- fifo的使用，在Altera的开发工具(fifo use in Altera's development tools)
traffic
- 交通灯设计，用verilog语言来实行，不包含设计原理图(aknsh s kjsf kwfh jfls ljfsl s lfjls jlsj ls jlf l ljfs ljljl f jljl ljjlsfj ljlsfj ljsflhig)
counter
- 计算器的verilog语言程序代码。能实现加、减、乘、除运算。-verilog language of counter。it can achiev plus o, minus, multiplication and addition operations
iir
- iir filter creat by altera
BPSK
- Binary phase shift keying in Xilinx system generator
Memory_tpf4
- Designing a memory in verilog
base_fir
- 使用verilog 写的FIR滤波器，里面并有matlab程序，是从altera官网下来的。。希望对大家游泳。-Use verilog to write the FIR filter, which have matlab and procedures, are down from the official website of the altera. . Everyone would like to swim.
code_element
- 总线控制器中接收部分的码元调制程序，希望能给大家带来帮助！-Bus controller to receive part of the symbol modulation process, I hope to give us some help!
jiaotongdeng-
- 普通交通灯，可以设置初始倒计时时间，用矩阵键盘设置。内涵原理图。请用proteus 7.7或者更高版本打开-Ordinary traffic lights, can set the initial countdown time, using matrix keyboard Settings. Connotation principle diagram. Please use proteus 7.7 or higher version open
jiaotongdeng
- stc89c51编写的交通灯程序并用protues仿真实现-stc89c51 write traffic light program and the protues simulation
1602-1
- 主要是很多单片机的简单模块的一些编程，功能完整，简练，-Many microcontroller mainly some simple module programming, functional integrity, concise,