资源列表
div_f
- --学习分频原理，在LED上面显示出来。一亮一暗 --利用计数器分频，把50MHZ的频率变的更慢。我们眼睛可以分辨的出来。 --输出是1Hz-- Learning divider principle, above the LED display.- The use of counter divider light up a dark 50MHZ frequency becomes slower. Our eyes can distinguish.- Output is 1Hz
Xilinx-ISE-and-Modelsim
- 详细的Xilinx ISE与Modelsim联合仿真平台搭建流程及简单实例操作演示，图文并茂，对于平台的搭建具有很好的指导性-Detailed Xilinx ISE and Modelsim joint simulation platform build process and a simple instance of the operating demonstration, illustrated, and have a very good platform to build
Verilog-code
- 基于cyclone 内核的fpga的源代码，带quartus2下载文件-Based on the source code of the cyclone kernel fpga, with quartus2, download files
micro-processor
- 这是一个8位微处理器的vhdl设计代码。-This is the design of a 8-bit micro-processor.
AES Algorithm
- The source codes describes the AES Algorithm
RSA codes
- the uploaded version contains codes of rsa algorithm
verilog
- opencore can bus verilog design file-opencore can bus verilog design file
siweijiafaqi
- 四位二进制加法器，用四个拨码开关表示四位二进制被加数，另外四个拨码开关表示四位二进制加数，进位和显示在5个数码管上。-Four-bit binary adder with four DIP switches four binary summand represents four binary addend another four DIP switches carry and display 5 digital tube.
yuequyanzou
- 乐曲演奏，使用quartusⅡ软件平台实现乐曲‘梁祝’的演奏。-Musical quartus Ⅱ software platform to realize the song ' Butterfly Lovers' playing.
fenpinqi
- 模拟分频器是音箱内的一种电路装置，用以将输入的模拟音频信号分离成高音、中音、低音等不同部分，然后分别送入相应的高、中、低音喇叭单元中重放。之所以这样做，是因为任何单一的喇叭都不可能完美的将声音的各个频段完整的重放出来。-The analog divider speakers within a circuit device to the input analog audio signal is separated into different parts of the treble, alto,
cordic3
- 利用cordic计算三角函数的verilog程序和modelsim仿真-To use cordic calculated trigonometric verilog program and simulation
jiaotongdeng
- Verilog编写的交通灯程序，Altera公司的DE2开发学习板。-Verilog prepared by the traffic lights program, Altera' s the DE2 development of learning board.