资源列表
CHENLI_VHDL_FINAL
- 四个按钮代表加法，减法，乘法和输入。也有8个二进制开关，用于输入两个操作数为每个计算。四位十六进制显示所选择的操作数和计算结果。-You will design a hexadecimal calculator.four push buttons represent Addition, Subtraction, Multiplication and Enter. There are also eight binary switches used to enter two operands for
two-of-the-state-machine-written
- 文档中主要介绍状态机的两种写法--竖着写(在状态中判断事件)和横着写(在事件中判断状态)。-The document introduces two of the state machine written- bristling write (write (in the incident to determine the state judge in the state in the event) and sideways).
VHDLproject-by-Qian-Yu
- 创建一个实时的视频处理器采用了FPGA技术的系统设计与VHDL。在这个项目中，我们实现滑动窗口滤波器，Sobel算子，一系列传感器和数字显示器VGA模块。-create a real-time video processor using FPGA technology in the course System Design with VHDL. In the project we implement modules for sliding window, sobel lter, a ran
7segment-display-VHDL
- 使用的NEXYS2原型设计电路板的7段编码器模拟-using the NEXYS 2 prototyping board Simulate the 7-segment encoder
adc0804
- 从ADC0804 的通道IN+输入0~5V 之间的模拟量，通过ADC0804 转换成数字量在数码管上以十进制形成显示出来。-From the ADC0804' s channel IN+ analog input between 0 ~ 5V through ADC0804 conversion to digital, digital tube to decimal form is displayed.
data_gen
- 产生随机的prbs序列。用于receiver的测试。误码率的测试等待-Generates random prbs sequence. For receiver testing. BER test wait
Altera-FPGA-TimeQuest
- 在Altera的FPGA中实现高速Link口的时序约束方法-The timing constraints Methods in Altera' s FPGA to achieve high-speed Link port
SPI_fpga_w_r_sigle
- verilog fpga spi slave 收发测试 有简单的协议 modelsim仿真通过 -simple protocol modelsim verilog fpga spi slave transceiver test simulation by
Verilog
- 学习快速入门verilog的程序 学习verilog必备 非常全面 共包含42个实例代码-Learn QuickStart verilog program learn verilog essential very comprehensive example code contains a total of 42
exp_r_alu
- 总线传输实验，包含下载到实验箱验证,数码管。二极管显示-Bus transfer experiments, contains downloaded to the validation of the test box, digital tube. Diode display
VHDL
- 基于VHDL语言的交通灯设计:通过状态机设计实现交通灯的红黄绿三种灯显示.其功能包括:红绿黄灯显示,倒计时功能,测试功能,手动控制功能.-Based on VHDL design of traffic lights: red, yellow, and green traffic lights, three lights through the state machine design features include: red, green, yellow, countdown function
zongxianchuanshu
- 湖南大学总线传输实验 原理图及仿真结果-Hunan University bus transfer experimental experimental schematics and simulation results