资源列表
aes
- aes加密算法的Verilog语言实现（顶层代码，已编译，无错误）-aes encryption algorithm of Verilog language (top-level code, compile, no error)
DE2_70_TV
- de2 70 开发板的演示程序，verilog语言编写，视频输入输出-de2 70 development board demo program, verilog language written, video input and output
s-box
- 用Verilog语言描述的des的s盒（des s盒 Verilog代码） -Verilog language descr iption des s box (des s box Verilog code)
des
- des的Verilog代码（已编译，可直接使用）-des Verilog code (compiled, and can be used directly)
des3
- 3des的Verilog代码（已编译，可直接使用）-3des Verilog code (compiled, and can be used directly)
rsa_top
- rsa的顶层代码（用verilog编写，已编译）-the rsa the top level code (written in verilog compiled)
traffic
- 模拟交通灯变化过程控制的VHDL程序，用红黄绿LED灯表示交通灯，用数码管显示状态剩余时间-Control procedures and VHDL simulation traffic lights change process, with red, yellow, and green LED lights, traffic lights, with a digital display of the status of the remaining time
FPGA
- 此程序是FPGA入门程序，可实现跑马灯亮-This program is FPGA Starter program, Marquee bright
Waveform-generator
- 波形发生器（含test beach）VHDL语言编写-Waveform generator (including test beach) VHDL language
Stepper-motor-controller
- 步进电机控制器 (VHDL语言编写)亲自尝试可运行-Stepper motor controller VHDL language
load--clr-register
- 带load、clr等功能的寄存器 VHDL语言编写，亲自运行，成功-Register VHDL language, with features such as load, clr personally run
The-various-functions-of-the-counter
- 各种功能的计数器VHDL语言编写，亲自运行，无错-The various functions of the counter VHDL language, personally run error-free