资源列表
div_any
- 任意整数N分频器的verilog代码，N需要代码中进行设置-Any integer N divider verilog code N need to code set
05_UART_demo
- 该UART实例是很简单的EDK工程，在PLB总线上挂载了XPS-uartlite外围设备，作为串口的控制器，一般的EDK工程会将该IP作为基本外围设备来使用。包含bit流文件(在EDK上下载到FPGA上使用），和说明文档。-The UART instance EDK project is very simple and is mounted on the PLB bus the XPS-uartlite peripherals, general EDK works as a serial con
cpu-risc
- wb_switch，cpu设计，精简指令cup设计-wb_switch，opencore，risc cpu design。
wb_switch
- wb_switch，opencore，精简指令cpu设计-wb_switch，opencore，risc cpu design。
sw_leds
- 精简指令cpu设计，外扩电路设计，led开发板驱动-wb_sw_leds，opencore，risc cpu design。
display-seg
- 七段数码管驱动电路，fpga，seg7，altera开发板例子-risc-cpu design，seg7，fpga
Yeni-WinRAR-archive
- vhdl defination beginning starter
SPWM-output
- 利用FPGA，采用DDS技术产生具有死区控制的SPWM波-To utilize FPGA, generation of DDS technology with deadband control SPWM wave
Lamp-from-left-to-right
- 接在P0口的8个LED从左到右循环依次点亮，产生走马灯效果-Then were lit in P0 port 8 LED from left to right cycle, resulting in a revolving door effect
Verilog
- verilog语法,硬件FPGA编程的工具-the verilog syntax, hardware FPGA programming tools
lift
- 运用VHDL实现可控三层电梯 利用LED和点阵表示电梯的上下 与楼层显示-Use VHDL to achieve controllable three elevator use of LED and dot matrix, said the elevator up and down the floor display
lab_3
- Verlog HDL实现m序列检测“1010”，如果有，则输出一个高电平-The m sequence detection, " 1010" Verlog HDL, if there is a high output