资源列表
assg-2-2-code-converter
- CODE CONVERTER IN VHLD ,Binary to Gray using structural modelling of XOR Gate
counter60
- Verilog语言编写的模60计数器和testbench-Verilog language model 60 counters and testbench
DE2_NIOS_DEVICE_LED
- Verilog代码，适合于初学者进行学习，是基于DE2平台的代码。
half-adder
- 半加器 东北大学秦皇岛分校 电子设计自动化 实验-Half adder Northeastern University at Qinhuangdao electronic design automation experiment
sdramcore
- sdram控制的内核，高手编的，已经调试过了，没有错误-SDRAM control of the kernel, the top series, has been tuned, no errors
LCD1602
- lcd1602 4线8线驱动函数，包括keil工程，已在stc89c52rd+12mhz测试通过，可直接用-lcd1602 4-line 8-line-driven functions, including keil project has been tested in stc89c52rd+12 mhz, can be directly used
verilog
- 经典verilog实例，将近130多个。包含大部分设计基础实例，有益于初学者学习。-Classic example of verilog, nearly more than 130. Contains examples of most of the design basis, the benefit of beginners learning.
FIR
- FIR在FPGA中的VHDL代码实现教程-FIR in FPGA code in VHDL Tutorial
Avalon_PWM_IP_pwm.rar
- Avalon总线下的PWM的IP模块。基于VHDL语言。,Avalon Bus IP of the PWM module. Based on the VHDL language.
DES
- This is verilog source code for DES(Data Encryption standard) which is used in network security.
tanchishe
- verilog编写的贪吃蛇小游戏，能够在vga上显示，可以通过sp3键盘控制蛇的运动，吃食物-verilog prepared by the Snake game, vga on display by sp3 keyboard to control the movement of the snake to eat the food
Blackjack
- Blackjack program VHDL program SystemVerilog