资源列表
additionneurcomplet
- additionneur complet
comparator_2
- General digital comparator
CRC_16
- crc16的串行和并行写法，而且有详细的测试文件-Serial and parallel crc16 written, and detailed test documents
wtut_edif
- Xilinx clock. DIGITAL CLOCK for Spartan-3 Starter Board. This design shows how to generate a digital clock and display the output to the multiplexed 7- segment display in VHDL.
tugas-1
- Coding VHDL Substractor adder
usb2.0-verilog-hdl
- usb2.0协议层的verilog hdl实现-usb2.0 protocol layer implementation verilog hdl
Hex2Verilog
- 《基于VHDL的FPGA与NIOS II实例精炼》第十八章 UART核的应用 - 视... -《基于VHDL的FPGA与NIOS II实例精炼》第十八章 UART核的应用- 视...
wb_conbus
- wishbone的verilog代码的实现，标准的协议规范-wishbone of the verilog code implementation, the standard protocol specification
jtag_atlantic_terminal
- jtag communication between on chip jtag_uart and PC host
SPI_VHDL
- this the simple of CC25oo verilog HDl code for FPGA thank you-this is the simple of CC25oo verilog HDl code for FPGA thank you
fifo
- 异步FIFO的VHDL程序，已经通过quartus编译和仿真。 -Asynchronous FIFO, VHDL program, has been compiled by quartus and simulation.
clock
- 闹钟系统的控制 闹钟系统的移位寄存器 闹钟系统的闹钟寄存器和时间计数器 闹钟系统的显示驱动器 闹钟系统的分频器 闹钟系统的整体组装-Alarm system, alarm system control shift register alarm system alarm registers and the time counter display driver alarm system, alarm system, alarm system, the overall a