资源列表
lab_1
- verlog HDL 实现3比特加法器 附带测试与限定文件-verlog HDL 3-bit adder with a test and qualified file
lab_2
- VHDL 实现M序列发生器 附带测试与限定文件-M-sequence generator VHDL incidental test with limited file
jzjpjsq_jiajianchengchu
- 基于Max+plus2软件Verilog VHDLy语言的矩阵键盘的加减乘除，在数码管上显示相关数据-Matrix keyboard, Math Max+plus2 software the Verilog VHDLy language, the relevant data is displayed on the digital
miaobiao
- 基于Max+plus2软件的Verilog VHDL语言的按键控制数码管显示秒表-Based on Max+plus2 software Verilog VHDL language button control digital display stopwatch
duogongnengshuzizhong
- 基于Max+plus2软件的Verilog VHDL语言的数码管显示多功能数字钟-Multifunctional digital clock digital tube based on Max+plus2 software Verilog VHDL language
PS2
- 基于FPGA的键盘PS第二类编码方式的verilog解码程序。 -FPGA keyboard PS encoding the verilog decoding procedures. FPGA keyboard PS encoding the verilog decoding procedures.
traffic
- 实现交通灯的源码，并且在modelsim中仿真通过，测试后程序可行-The source of the traffic lights, and through simulation in modelsim test program feasible
38yimaqiforep8c35
- 38译码器，cyclone2ep2c35,altera公司，-38 decoder, cyclone2ep2c35, altera
myfifo
- 在quartus II上用宏功能模块编写的fifo先进先出寄存器功能-The fifo first-in, first-out register functions megafunctions written quartus II
q_74ls138
- 在quartus II 9.1上用verilog原理图形式实现的74ls138功能的38译码器-38 of 74ls138 features achieve verilog schematic form in quartus II 9.1 decoder
Counter10
- 在quartus 9.1软件上用verilog语言编写的10进制计数器程序-The Verilog language quartus 9.1 software 10 binary counter program
tanshishe
- 贪食蛇游戏。分模块编写，包含按键防抖模块，分频模块，随机数模块，点阵显示模块，数码管显示模块，控制模块。-Prepared by the sub-module contains button image stabilization module, frequency module, random number module, dot matrix display module, digital display module, the control module.