资源列表
synchronism_design
- 信号进入不同时钟域时的同步处理的例子，请有需要的借鉴参考-Example of the synchronization signal into different clock domains, there is a need to draw reference
Timing-Analysis
- 关于VHDL/VERILOG进行EDA设计时序分析时需要注意的一些需要注意的问题及处理策略，保证相当实用，请需要的人参考-VHDL/VERILOG the EDA design timing analysis need to pay attention to some issues that need attention and treatment strategies, guaranteed to be quite practical, please need Reference
uart_fifo_design
- verilog语言时序的异步读写FIFO，请需要者借鉴参考-the verilog language Timing asynchronous read and write FIFO, for those who need to learn from reference
FFT-transform
- 64位FFT变换源代码，仅供参考。此为单一模块文件，自行建立工程编译-64 FFT transform source code, for reference only. This is a single module file, create your own works compiled
Verilog
- 实现对文本的检测，实现关键字的过滤，开发工具 ISE14.1以上
Lab07
- LabVIEW FPGA Implementation of Convolution
Lab08
- LabVIEW FPGA Implementation of Digital Filtering
Lab09
- LabVIEW FPGA Implementation of Adaptive Filtering
Lab10
- LabVIEW Frequency Analysis in LabVIEW FPGA
Lab05
- LabVIEW Fixed-Point FPGA Implementation
UART
- 本论文使用Verilog HDL 语言描述硬件功能，利用QuartusII 5.0在 FPGA 芯片上的综合描述,采用模块化设计方法设计UART（通用异步收发器）的各个模块。-The paper using Verilog HDL language to describe hardware features, the use of the FPGA chip QuartusII 5.0 comprehensive descr iption of the modular design approa
Pdg2Pic
- 有关于VHDL的很好的资料，希望能帮上大家，自己学习过来的-Able to help on about VHDL good information, learning over