资源列表
deserialize-VHDL
- VHDL写的串并转换代码，经ISE13.3测试能用的。-VHDL to write a serial-to-parallel conversion code, can be used the ISE13.3 test.
digital-clock
- verilog实现数字钟功能，闹钟功能，日历功能-Verilog digital clock function, alarm clock function, calendar function
music
- verilog实现FPGA板的音乐播放功能，可调整不同乐谱-Verilog FPGA board music player, adjustable sheet music
taxi
- verilog实现出租车计费功能，起步价、里程数、等待时间计算-Verilog taxi meter function, starting price, mileage, waiting time
VHDL_SPI
- 很详细的SPI程序，VHDL代码写的。包含数据接收发送各部分代码。-SPI program, VHDL code written. Contain data transmission and reception of each part of the code.
cpld-urat-vhdl
- 基于CPLD的VHDL UART代码，串行异步通信，含代码及仿真图-Based on the CPLD VHDL UART code, serial asynchronous communication, including code and simulation diagram
1024-FFT-VHDL
- 1024点FFT的VHDL程序，含碟形图，旋转因子存储及产生代码，最后是VHDL整体设计，quartus ii编译环境-1024-point FFT VHDL program, including dish-shaped figure, twiddle factor , last VHDL overall design, Quartus ii compile environment
P1
- I don t speak english. Sorry.
verilogHDL
- 本文主要介绍了Verilog HDL 语言的一些基本知识，目的是使初学者能够迅速掌握HDL 设计方法，初步了解并掌握Verilog HDL语言的基本要素，能够读懂简单的设计代码并能 够进行一些简单设计的Verilog HDL建模。-This paper describes some basic knowledge of the Verilog HDL language, so that beginners can quickly grasp the HDL design methods,
verilog-HDL--LCD-display-
- 用verilog HDL 实现LCD显示-using verilog HDL to LCD display
shuzipinlvji
- 设计一个能测量方波信号的频率的频率计，测量的频率范围是0 999999Hz，结果用十进制数显示。 -Design a frequency meter measuring the frequency of the square wave signal, the measurement frequency range is 0 ~ In 999999Hz The results are shown in decimal.
Carry_Select_Adder_Verilog
- 进位选择加法器，verilog实现。包含3个TB。-Carry Select Adder. Verilog fulfilled. Three testbenches included.