资源列表
Visio-绘图21
- 这是asic流程例子.文件内容已经验证过.如有疑问和我联系-This is the process blends example. The contents of the documents has been proven. And I doubt if links
4.ripple.counter
- 4位 ripple的寄存器计数器，代码和设计图-4 bit ripple counter code and layout
codes
- vhdl code for sbst and channel encrptions
Example-4-1
- FPGA中存储器设计实例，包括设定与仿真，适合初学者使用-FPGA, memory design examples, including the setup and simulation, suitable for beginners
FPGA IP cores
- FPGA IP cores on verilog for USB CY7C68013, VGA, Ethernet DM9000A, Sound WM8731.
fifo_syn
- 本源码是用VERILOG实现FIFO的读取，并在实验板上已经验证可以使用-This source is used to achieve FIFO read VERILOG, and the board has been verified in experiments using
Copy-(2)-of-New-Microsoft-Word-Document
- pn random code gerator fast
DE2_VGA_pattern_gen
- 在vga上找到pattern的位置
Multi-networkvideocallsource
- 基于DE2的视频电话部分源码，实现了视频图像采集，VGA显示，局域网通讯等功能-DE2-based video telephony part of the source code to achieve the video image capture, VGA display, LAN communications function
Copy-of-New-Microsoft-Word-Document
- pn-random code generator
New-Microsoft-Word-Document
- general code for counter
use_SRAM_design_FIFO.pdf
- 利用sram技术设计的一个FIFO-failed to translate