资源列表
verilog--serial-port-communication
- 自己看了很多材料以后，精心整理的串口通信实验原理和指导，在网上找了很多代码，大部分因为没有很好的注释，看起来很头疼，于是自己写了一份，附带详细的注释，在modelsim仿真器上已经得到验证，现在传上来，仅供参考。-verilog codes for serial port communication
FPGA-port_Verilog_HDL
- CY7C68013与FPGA接口的Verilog HDL实现，经过本人实验检验过的，-CY7C68013 and FPGA interface Verilog HDL realize the experiment after I test
Berlekampalgorithm_Verilog_hdl
- RS编码器是Reed Solomon编码器的简称，它是目前最有效、应用最广泛的差错控制编码方法之一。-The RS encoder Reed Solomon encoder referred, it is the most effective, the most widely used error control coding method one.
asynchronous-FIFO-verilog
- FIFO是英文First In First Out 的缩写，是一种先进先出的数据缓存器，他与普通存储器的区别是没有外部读写地址线，这样使用起来非常简单-FIFO is an abbreviation of the English First In First Out, is a first-in, first-out data buffer, the difference between him and ordinary memory is external read and write add
DECODER416
- 4-16 译码器（4 输入16 输出译码器）-4-16 decoder (4-bit input 16-bit output decoder)
uart_lcd
- 基于FPGA的UART通信，并用LCD(1602)显示通讯状态和通讯的数据。通过在ALTERA公司生产的DE2-115开发板上运行，证明此程序稳定可靠。时钟为50MHz，语言为VHDL,状态机。-FPGA-based UART communication, and LCD (1602) show the communication status and data communications. DE2-115 development board by ALTERA Company product
edashuzipinlvji
- EDA/VHDL数字频率计，可编程逻辑门阵列，EDA课程设计-EDA/VHDL digital frequency meter, programmable logic gate array, EDA curriculum design
CopperHoleTest3.17
- 一个简单的状态机，用来实现一个操作流程和8段码的显示及老化控制-A simple state machine, used to implement the display of an operation process, and 8 code
FULL
- Full code for fused floating point operations.
ADD_UNIT
- floating point add unit
SUB_UNIT
- floating point subtract unit
ADD_SUB
- floating point fused add-subtract unit