资源列表
bch_dec
- BCH编解码 Features : – allows to correct up to 2 errors. – supports 16/32/64/128 bit memories (typical memory word sizes). – operates on complete memory words in a single cycle. – pure combinational logic design-The double error correcting (DE
rs232
- 串口传输，传输协议为RS232。RS-232C标准是美国EIA（电子工业联合会）与BELL等公司一起开发的1969年公布的通信协议。-Serial transmission, the transmission protocol for RS232. RS-232C standard communication protocol is developed with the EIA (Electronic Industries Association) BELL companies in the U
32_by_8_RAM
- 32*8 RAM。Verilog实现。包含TB。-32 by 8 RAM. Testbench included.
m_seq
- Verilog HDL 实现的4位二进制 16个m序列产生-Verilog HDL m_seq
C6416DSK
- dsp图像处理程序 imlib库等的使用技巧-DSP image processing program imlib library use skills
internet_test
- xilinx SP605 板卡，网口设计。echo设计，实现接收单字符并返回的功能，同时从串口显示输出内容-Xilinx SP605 board, network port design. echo design, implementation, receiving single character and returns the output from the serial port at the same time
count-1
- 基于Verilog的仿真，各个进制的计数器仿真。-Verilog-based simulation, the simulation hex counter.
mywork
- nexys 3 板卡，打砖块游戏。连上VGA接口，然后将mywork文件夹里的所有内容考到一个新建的文件夹下，不要有中文目录。下载运行就行了。-Nexys 3 board card, Arkanoid game. Connected to the the VGA interface, and then will mywork file folder li the all the contents of test to the a the newly created file folder und
taxi
- 出租车计价器，EDA课程相关实验，quartus ii -Taxi meter EDA course experiment, the Quartus II
adder16_2
- １６位２级流水线加法器的ｖｅｒｉｌｏｇ设计-16 2 pipeline adder Verilog design
ade
- 用verilog HDL语言实现一个8位串行乘法器-An 8-bit serial multiplier with Verilog HDL language
mul_addtree
- 用verilog HDL语言实现一个4位的流水线乘法器-Achieve a 4-bit pipelined multiplier using Verilog HDL language