资源列表
fsq
- 利用VHDL语言实现信号发生器。 -VHDL SIGNAL GENERATE
FPGASERIALPORT
- 利用VHDL语言实现串口通信，本程序经过调试可以正常使用。-VHDL SERIAL PORT COMMUNICATION
fifo_vhdl
- FIFO using vhdl and aslo configurable
VGA_char_ROM_success
- Verilog HDL语言编写的基于M4K块配置ROM的字符数据存储VGA显示实验代码，引脚分配适用于21EDA的EP2C8Q208开发板, 详细解说请参见特权同学《深入浅出玩转FPGA》视频教程中的《Lesson30：SF-EP1C开发板实验9——基于M4K块配置ROM的字符数据存储VGA显示实验》-experimental code written in Verilog HDL language，ROM configuration based on M4K block for the cha
shigfr
- 循环移位，实现cpld控制dac的数据采集，分时传输来那个词数据-Cyclic shift, to achieve control dac cpld data collection, sharing of data transmission to the word
kangxingongsi
- 康芯公司的培训内容，内含很多FPGA的使用事项和经验教习，希望多大家有所帮助。-The core of company training contents of Cornwall, containing many FPGA use and experience, hope everybody toupees and help.
plpp_answers
- Programming Languages - Principles and Practice 2nd Edition by Kenneth C. Louden Thomson Brooks/Cole 2002 Answers to Selected Exercises
lift
- 用VHDL编写的全功能四层电梯控制器-Prepared with a fully functional VHDL four elevator controller. . .
flushpcnisee
- soil structure interaction analysis program from NIS-soil structure interaction analysis program from NISEE
ppt
- Verilog课件,包括概论。语法。-verilog ppt include introduction，semantics and so on
PCB_Project1.~(1).PrjPCB.Zip
- 51MCU & CPLD EZ-KIT实验开发板--
log32
- Logarithm 32 bit written in VHDL and implemented in Xilinx