资源列表
alog32
- 32 bit antilog coding. Completely synthesizable. Tested in spartan 3A DSP series
logmultiplier
- Multiplier based on Logarithm. Completely synthesizable. Tested in spartan 3A DSP series
sbiu_phase_1
- VHDL SYSTEM VERILOG CODES
uart
- vhdl语言的串口发送/接收模块，本人用在多个工程，很好用。-vhdl language of the serial transmit/receive module, I used a number of projects, very good use.
2010xcsj
- 逆变器SPWM程序，可以拿来参考一下，还是很有价值的-SPWM inverter program that can bring information about, or of great value
GOODRLS
- RLS 算法，很方便的，新手看看，对你应该有帮助。-RLS
vb1
- VB编写的仿真实电子琴操作界面，包含与FPGA串口通信的功能-VB, real keyboard simulation interface, contains the FPGA serial communication function
FPGAexamplesofcode
- FPGA应用开发入门与典型实例代码，典型实例5_1 交通灯控制器-FPGA Application Development and Typical examples of code, a typical example of traffic light controller 5_1
5546546516
- ARM,DSP,FPGA 的解释与说明A RM,DSP,FPGA 的解释与说明-ARM,DSP,FPGA ARM,DSP,FPGA ARM,DSP,FPGA
FPGAkaifa
- 赛灵思的FPGA的ISE和EDK软件入门学习和基本使用方法-the introductory learning and basic use of xilinx of the EDK and FPGA ISE
lk
- 这是vhdl语言编写 实现六十计数的 -It is written in vhdl to achieve 60 counts
FREQENCYrar
- 这是用DDS原理实现的频率计，能够测量1到999999HZ的待测信号，包括VHDL源程序以及成型的BDF文件。-This is achieved with a frequency meter DDS principle, can measure a signal under test to 999999HZ, including VHDL source code, as well as forming the BDF file.