资源列表
Audio_DAC_FIFO
- 用于做多媒体缓存的源码 可以做整帧的缓存-SquiDeral- manipulating the cache usage of Your Audio.
qpsk_demod_use_FPGA
- 根据软件无线电的思想，提出了一种新颖的数字信号处理算法，对QPSK信号的相位进行数字化处理，从而实现对QPSK信号的解调.该算法允许收发两端载波存在频差，用数字锁相实现收发端载波的同步，在频偏较大的情况下，估算频偏的大小，自适应设置环路的带宽，实现较短的捕获时间和较好的信噪性能。整个设计基于XILINX公司的ISE开发平台，并用Virtex-II系列FPGA实现。用FPGA实现调制解调器具有体积小、功耗低、集成度高、可软件升级、扰干扰能力强的特点，符合未来通信技术发展的方向。-According
fsk_completed
- FPGA为设计载体，VHDL 为设计输入，完成2FSK调制器的实现，下载到DE2平台通过D/A转换模块于示波器上实现-2FSK based on Fpga
MII
- 以太网MII芯片配置接口的VHDL设计，配置PHY芯片的模块设计-Ethernet MII chip configuration interface VHDL design, configuration PHY chip module design
mul1
- n*n pipeline multipler
6416_dsk_vhdl
- this file is vhdl file of dsk6416 cpld vhdl file
fp_adder
- this a code for implimenting floating point adder on FPGA -this is a code for implimenting floating point adder on FPGA
PWM_Module
- Very clean design of a PWM module made in structural VHDL. Lower blocks are behavioral.Designed in Quartus 9.0,
filtro_hdlcoder
- Example project of a filter designed in MATLAB and exported to VHDL.
Dip_PB_LED
- 4 bit counter. 1 Push Button (PB) and 1 Dip Switch (DP)are inputs. 4 Leds (common anode) are outputs.
ADC
- analog to digital converson programmed in VHDL
rs232_receive_control
- RS232 receive control in VHDL