资源列表
Verilog_HDL
- verilog的学习很重要的教程，有很大的好处。-verilog tutorial learning is important, a great advantage.
responder
- 实现四路抢答器功能，主持人可以控制抢答开始，也可以将各个抢答器清零-Responder function to achieve four-way, the host can control the answer in the beginning, you can also clear the various Responder
test8
- 设计一个8路数据选择器，每路输入数据与输出数据位四位二进制的-Design of an 8-channel data selectors, each data bit input data and output four binary
caiseqianbihua
- 彩色铅笔画的绘制过程，运用交互式着色的方法-Colored pencil drawing process, the use of an interactive method of coloring
xdtxylysj
- 一本很好的讲解通讯方面的书籍,主要包括电话通信网，移动通信网-a very good book that intoduce the knowledge of communication
altera_fft
- verilog实际例子，非常适合初学者学习-verilog practical examples, very suitable for beginners to learn
chumoping(Verilog)
- verilog实际例子，非常适合初学者学习-verilog practical examples, very suitable for beginners to learn
ds112
- xilinx Virtex-4简介 三个系列 - LX/SX/FX - Virtex-4 LX：高性能逻辑应用解决方案 - Virtex-4 SX：高性能数字信号处理 (DSP) 应用解决方案 - Virtex-4 FX：高性能全功能嵌入式平台应用解决方案-Virtex-4 Family Overview
keyboardcontroller_latest.tar
- keyboard controller vhdl
ddslabview
- The reference design and example presented in this article illustrates how you can add a DDS (direct digital synthesis) waveform generator to your LabVIEW FPGA based applicationThe examples for this article are contained in a LabVIEW 8.5.1 project.
CoolRunner
- This the default CPLD design shipped with the board. The CPLD helps reduce the number of jumpers on the board and simplifies the interaction of all the possible FPGA configuration memory sources-This is the default CPLD design shipped with the board.
spislave_latest.tar
- SPI接口的verilog代码，本代码是从机代码。-SPI interface verilog code, the code is slave machine code.